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lt3804 1 3804i information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. final electrical specifications n regulates two secondary outputs n optocoupler feedback driver and second output synchronous driver controller n true differential remote sensing regulation n high switching frequency: up to 800khz n programmable current limit n programmable soft-start and power good n automatic frequency synchronization n available in thermally enhanced 28-lead tssop applicatio s u features descriptio u typical applicatio u the lt ? 3804 is a high efficiency step-down switching regulator with optocoupler feedback control for regulating multiple outputs in single-secondary winding isolated power supplies. the lt3804 contains an error amplifier and an optocoupler driver to regulate the first (main) output. for the second output regulation, the lt3804 contains a complete pwm controller to drive dual synchronous n-channel mosfets. with leading edge modulation, it operates with either current or voltage mode control of the primary side. the lt3804 is synchronized to the falling edge of the trans- former secondary winding and can be used in single- ended or double-ended isolated power converter topolo- gies. a user selectable discontinuous conduction mode improves light load efficiency. true differential kelvin sensing is used for each output feedback amplifier to achieve high regulation accuracy and design simplicity. other features include soft start, current limit and power good flags. , ltc and lt are registered trademarks of linear technology corporation. n 48v input isolated dc/dc converters n multiple output power supplies n offline converters n dc/dc power modules secondary side dual output controller with opto driver june 2003 in2 in1 out2 out1 v cc bias v out1 3.3v at 15a bg sg lt3781 isolation boundary c out1 , c out2 : sanyo poscap 4tpe680mf 680 f/4v l1, l2: sumida cep125-ir8mc-h q1-q4: siliconix si7892dp v in 36v to 72v v ref v c v fb tg q1 q2 l2 1.8 h 0.003 + v out2 1.8v at 15a c out1 + ltc1693-1 cl1n cl1p v cc cset gnds1 v fb1 v aout1 opto sync tgate sw bgate pgnd cl2n v fb2 q4 x2 x2 q3 cl2p v aout2 gnds2 c out2 + l1 1.8 h v os1 + v os1 v os1 + v os1 1.5k 3.01k 604 lt3804 2.74k 390pf 3804 f01 0.003 figure 1. 250khz, 3.3v and 1.8v output isolated dc/dc converter (simplified schematic)
lt3804 2 3804i v cc supply voltage .................................................. 26v boost pin voltage with respect to sw pin ............ 10v boost pin voltage with respect to gnd pin .......... 35v sync pin voltage (note 2) ..................................... 30v gnds1 pin voltage ................................................... 1v gnds2 pin voltage ................................................... 1v operating junction temperature range lt3804e (note 3) ..............................C40 c to 125 c storage temperature range ..................C65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 125 c, q ja = 38 c/w exposed pad is sgnd (pin 29) must be connected to pcb lt3804efe absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 11v, gnds1=gnds2=0v, operating maximum v cc = 25v, no load on any outputs, unless otherwise noted. consult ltc marketing for parts specified with wider operating temperature ranges. fe package 28-lead plastic tssop 1 2 3 4 5 6 7 top view 28 27 26 25 24 23 22 8 9 10 11 12 13 14 21 20 19 18 17 16 15 cl1p cl1n i lcomp2 boost tgate sw cset sync ss2 pgin1 pgin2 gnds2 gnds1 v fb2 i lcomp1 gbias bgate v cc pgnd opto v aout1 cl2n cl2p pgood v fb1 ss1 bgs v aout2 29 parameter conditions min typ max units overall supply voltage (v cc ) l 825v supply current (i vcc )v aout2 1.2v (switching off) 9 13 ma boost pin current v boost = v sw + 8v, 0v v sw 24v tgate high 2 3 ma tgate low 2 3 ma voltage amplifier v a1 ,v a2 reference voltage (v ref1 ,v ref2 ) common mode: 20mv (0 c to 125 c) 0.591 0.6 0.609 v (C40 c to 125 c) l 0.587 0.609 v d v ref over common mode: 100mv C3 3 mv v fb1 , v fb2 pin input current v fb1 = v ref1 , v fb2 = v ref2 0.2 0.5 m a remote ground pin (gnds1,gnds2) current C100mv gnds1, gnds2 100mv l C50 C100 m a v aout1 high at oa1 threshold 1.5v v fb1 = v ref1 C 10mv, i vaout1 = C50 m a 1.75 v v aout1 high at oa1 threshold 1.25v v fb1 = v ref1 C 10mv, i vaout1 = C50 m a 1.45 v v aout1 low v fb1 = v ref1 + 10mv, i vaout1 = 100 m a 0.7 v v aout2 high v fb2 = v ref2 C 10mv, i vaout2 = C50 m a 4.5 v v aout2 low v fb2 = v ref2 + 10mv, i vaout2 = 100 m a 0.8 v v aout1 source current l 100 230 400 m a v aout2 source current l 70 150 250 m a open-loop gain 100 db gain bandwidth product 10 mhz soft-start current (ss1,ss2) 51024 m a
lt3804 3 3804i electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 11v, gnds1=gnds2=0v, operating maximum v cc = 25v, no load on any outputs, unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: if highter than 30v on sync pin is needed, add a 10k w resistor in series with the pin. note 3: the lt3804e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. parameter conditions min typ max units opto driver amplifier oa1 oa1 upper threshold l 1.4 1.55 1.65 v oa1 threshold hysteresis 0.25 v oa1 voltage gain (v opto /v aout1 ) 1.2v < v opto < 4v, r opto = 1k l 5.6 6 6.4 v v opto high v aout1 = 0.9v, i opto = C10ma l 4.5 5.2 6 v v opto low v fb1 = v ref1 C 10mv, r opto = 1k l 0 0.1 0.25 v i opto short-circuit current limit v fb1 =v ref1 C 10mv, gnds1 = 0v, v opto = 4v l C50 C25 C12 ma power good power good window threshold (pgin1-gnds1, pgin2-gnds2) C100mv < gnds1, gnds2 < 100mv 0.85 1.15 v ref input current (pgin1,pgin2) 0v < pgin1, pgin2 < 1v 0.2 0.35 m a delay time for power bad 25mv overdrive on pgin1,pgin2 l 100 200 300 m s output low (pgood) 2ma into the pin l 150 300 mv current limit amplifier ca1, ca2 current limit threshold (cl1p-cl1n, cl2p-cl2n) common mode voltage from 0v to v cc C 2.5v v aout1 = 1.2v, v aout2 = 2.5v, l 40 50 60 mv bgate off threshold at (v cl2p -v cl2n ), bgs pin float commond mode voltage from 0v to v cc C 2.5v 0 8 15 mv switching off threshold at i lcomp2 v ilcomp2 0.15 v input current (cl1p, cl1n, cl2p, cl2n) v cl2p = v cl1n , v cl2p = v cl2n 100 m a oscillator switching frequency c s = 500pf (no sync) l 170 200 240 khz c s = 333pf (no sync) l 240 280 340 khz c s = 200pf (no sync) l 400 470 570 khz synchronization frequency range c s = 500pf l 245 400 khz c s = 333pf l 345 500 khz c s = 200pf l 575 800 khz cset ramp valley voltage c s = 1000pf (no sync) 0.90 1.15 1.4 v cset peak-to-peak voltage c s = 1000pf (no sync) 2.4 v synchronization pulse threshold on sync pin falling edge v sync 2.5 v maximum duty cycle v fb2 = v ref2 C 5mv, c s > 333pf l 75 80 % gate drivers (tgate, bgate) v gbias i gbias < 25ma l 7.5 8 8.5 v v tgate high (v tgate C v sw )i tgate < 50ma, v boost = v gbias C 0.5v 5 6 7.5 v v bgate high i bgate < 50ma l 5 6 7.5 v v tgate low (v tgate -v sw )i tgate < C50ma l 0.5 v v bgate low i bgate < 50ma l 0.5 v peak gate drive current 10nf load 1 a gate drive rise and fall time 1nf load 25 ns
lt3804 4 3804i v gbias vs i gbias over junction temperature i cc vs v cc (switching off) voltage amplifier v a1 , v a2 gain and phase d v ref vs v cc , d freq vs v cc cset vs switching frequency v ref vs temperature switching frequency vs temperature g bias vs i gbias (charging 2.2 m f) current limit amplifier ca1 gain at v cc = 11v, v cl2n = 5v typical perfor a ce characteristics uw i gbias (ma) 0 v gbias (v) 8.1 8.0 7.9 7.8 7.7 3804 g01 10 20 26 ?0 c 25 c 125 c v cc (v) 8 1012141618202224 i cc (ma) 13 12 11 10 9 8 7 6 5 3804 g02 t a = 25 c frequency (hz) 10 gain (db) 120 80 40 0 ?0 phase (deg) ? ?0 100 150 180 3804 g03 phase 0db, 10mhz (?11 ) gain 100 1k 10k 100k 1m 10m 100m t a = 25 c v cc (v) 10 15 20 25 ? v ref (mv) 3 2 1 0 ? ? freq (khz) 1 0 ? 3804 g04 ? v ref cset = 500pf t a = 25 c ? freq time 0 i gbias (ma) 300 250 200 150 100 50 0 v gbias (v) 12 10 8 6 4 2 0 500 s 3804 g08 1ms v gbias c gbias = 2.2 f t a = 25 c i gbias v cl2p ?v cl2n (mv) 40 30 50 60 70 v aout2 (v) 8 7 6 5 4 3 2 1 0 3804 g09 cset peak v cc = 11v v cl2n = 5v t a = 25 c cset valley cset (pf) frequency (khz) 400 500 600 700 800 900 1000 3804 g05 100 200 300 800 600 400 200 1.00 0.95 0.90 0.85 0.80 0.75 0.70 cset maximum duty cycle maximum duty cycle t a = 25 c junction temperature ( c) ?0 v ref (v) 0.602 0.601 0.600 0.599 0.598 0.587 0.596 25 75 3804 g06 ?0 0 50 100 125 junction temperature ( c) ?0 switching frequency (khz) 215 210 205 200 195 25 75 3804 g07 ?0 0 50 100 125 cset = 500pf
lt3804 5 3804i cl1p (pin 1): current limit amplifier ca1 positive input. ca1 drives optocoupler when the first output is in current limit.the threshold is set at 50mv. cl1n (pin 2): current limit amplifier ca1 negative input. when used, cl1n is connected to the output, and cl1p is connected to the other end of the output current sense resistor. i lcomp2 (pin 3): current limit amplifier ca2 compensa- tion node. at second output current limit, ca2 pulls down on this pin to regulate output current. boost (pin 4): topside (boosted) driver supply.this pin is used to bootstrap and supply the topside power switch gate drive circuitry. in normal operation v boost is powered from the internally generated 8v gbias; v boost = v sw + 8v when tgate is on. tgate (pin 5): topside (boosted) n-channel mosfet driver. when tgate is on, the voltage is equal to v sw + 6v. sw (pin 6): switch node connection to inductor. cset (pin 7): oscillator frequency setting pin.the capaci- tor from this pin to ground sets the pwm switching frequency. sync (pin 8): synchronization input. this pin should be connected to the secondary side output of the power transformer with a series resistor. a filtering capacitor of 10pf is recommended. ss2 (pin 9): soft-start for the second output. a capacitor on this pin sets the output ramp-up rate. the typical time for ss2 to reach the programmed level is: (c ? 0.6v)/10 m a. pgin1 (pin 10): first output power good input.the volt- age setting resistor divider should be connected to gnds1 if remote sensing is used. pgin2 (pin 11): second output power good input. the voltage setting resistor divider should be connected to gnds2 if remote sensing is used. gnds2 (pin 12): second output remote ground sensing. gnds1 (pin 13): first output remote ground sensing. v fb2 (pin 14): voltage amplifier v a2 inverting input. a resistor divider to this pin sets the second output voltage. the reference voltage at this pin is v ref2 (0.6v referred to remote sensing ground gnds2). v aout2 (pin 15): voltage amplifier v a2 output. bgs (pin 16): bottom gate switching control. ca2 moni- tors the inductor current and prohibits bgate from turn- ing on when the inductor current is low (below 8mv across the current sense resistor r s2 ) allowing discontinous mode operation and avoiding reverse inductor current. grounding bgs disables this function, so that the pwm is always in continuous mode except during start-up. ss1 (pin 17): soft-start for the first output. a capacitor on this pin sets the output ramp-up rate. the typical time for ss1 to reach the programmed level is: (c ? 0.6v)/10 m a. v fb1 (pin 18): voltage amplifier v a1 inverting input. a resistor divider to this pin sets the first output voltage. the reference voltage at this pin is v ref1 (0.6v referred to remote sensing ground gnds1). pgood (pin 19): power good. pgood goes high to indicate power good only when both pgin1 and pgin2 sense power good. a pull up resistor is required on this pin if the power good function is used. cl2p (pin 20): second 0utput current limit amplifier ca2 positive input.the threshold is set at 50mv. cl2n (pin 21): current limit amplifier ca2 negative input. when used, cl2n is connected to the output capacitor, and cl2p is connected to the other end of the output current sense resistor. v aout1 (pin 22): voltage amplifier va1 output. opto (pin 23): optocoupler driver. a resistor to the opto diode is required to set the optocoupler bias current. maximum sourcing current is 10ma at 5v. pgnd (pin 24): ground of the bottom side n-channel mosfet driver. v cc (pin 25): supply of the chip. a low esr capacitor is required to bypass the supply. bgate (pin 26): bottom side n-channel mosfet driver. gbias (pin 27): 8v regulator output for boostrapping v boost . a bypass capacitor of at least 2 m f is needed. i lcomp1 (pin 28): current limit amplifier ca1 compensa- tion node . when the first output is in current limit, ca1 pulls down v aout1 pin to regulate the first output current. exposed pad (pin 29): signal ground. must be electrically connected on pcb. uu u pi fu ctio s
lt3804 6 3804i block diagra w + + + + + + shut- down + + + + 8v + + + e2 oa1 50mv ca q5 va1 d15 d14 10 a 200 a v ref1 0.6v 1.3v v cc v cc q1 r8 r7 c8 d2 lt3781 m3 m4 r11 opto opto opto r opto q3 isolation boundary v in 36v to 72v ss1 c ss1 1 f transformer secondary output a4 + + bgate a3 + + + sw a10 a8 + + ss2 a11 a13 2.5v 2.5v 3.5v 1.6v 7v + 8v 1.1v ref1 0.9v ref1 + + va2 d6 d7 10 a v ref2 0.6v 1.3v c9 c13 q2 pgood 200 s delay + + 1.1 v ref2 0.9 v ref2 c15 c14 q4 200 s delay i lcomp1 cl1p cl1n v aout1 i lcomp2 v aout2 v fb1 gnds1 pgin1 c17 200pf r12 c3 2 f c2 0.3 f r3 r4 r19 r20 r13 r14 r16 r17 load v out1 c out1 c out2 v out2 r1 r2 l2 l1 r s2 r s1 boost tgate sw gbias bgate pgnd bgs pgin2 cl2n cl2p v fb2 gnds2 pgood 8mv 50mv + m2 m1 + + + c12 500pf one shot osc ca2 c16 r s e4 a7 a2 pwm r s 10k c s 10pf cset sync agnd note: package bottom metal plate is fused to signal ground. c ss2 1 f ss2 9 29 12 15 3 21 20 16 24 26 27 6 5 4 19 10 13 18 22 2 1 28 25 23 17 8 7 r6, 5k c6, 100pf 2v ca1 a1 90k 15k 1.5v/ 1.2v v th 3804 bd a6 load 11 14 exposed pad
lt3804 7 3804i to generate isolated multiple outputs, most systems use either multiple secondary windings or cascade regulators for each additional output. multiple secondary windings sacrifice regulation of the auxiliary outputs. cascaded regulators require a larger inductor for the main output, because all of the power is processed in series. by gener- ating the auxiliary output(s) from the secondary winding of the main output, the lt3804 allows for parallel process- ing of the output power. this minimizes the main output inductor size and directly regulates the auxiliary output. with synchronous rectification, the system efficiency is greatly improved. the lt3804 regulates both the main and one auxiliary output, with true remote sensing to achieve high output accuracy. to regulate the first output, the lt3804 contains a high gain error amplifier va1 and an optocoupler driver oa1 with a unique feature that reduces output overshoot to a minimum. for details see the applications information section. the second output includes a voltage amplifier, va2, (see block diagram)a voltage mode pwm with trailing edge synchronization and leading edge modula- tion, a current limit amplifier, ca2, and high speed syn- chronous switch drivers. operatio u during normal operation (see figure 2), a switching cycle begins at the falling edge of the transformer secondary voltage v s . the internal oscillator is reset, turning off the top mosfet, m1, and turning on the bottom mosfet, m2. during this portion of the cycle, the inductor current is discharged by the output voltage v out2 . the transformer secondary voltage, v s , will go high during this portion of the cycle. since m1 is off, the switch node voltage, v sw , remains zero. the inductor current continues to be discharged by the output voltage v out2 . this condition lasts until the ramp signal intersects the feedback error amplifier output v aout2 . the top mosfet m1 turns on, pulling the switch node voltage to v s . the inductor current of the lt3804 circuit is then charged by v s C v out2 . the effective on time of this buck circuit ends when the secondary voltage becomes zero. the next cycle repeats. the ideal equation for duty cycle of the lt3804 is: d2 = v out2 /v sp where v out2 is the auxiliary output voltage, v sp is the amplitude of the secondary voltage and d2 is the duty cycle of the switching node voltage v sw , as defined in figure 2. figure 2. leading edge modulation, trailing edge synchronization transformer secondary voltage sync signal v reset ramp v cset switch node v sw 3710 f02 v aout2 tgate bgate i l2 d 1 t v sp v s v reset t d 2 t v sp t
lt3804 8 3804i synchronization and oscillator frequency setting the switching is synchronized to the secondary winding falling edge and the synchronization threshold is typically 2.5v. the synchronization falling edge triggers an internal inverted ramp (see figure 2) and starts a new switching cycle for the leading edge voltage mode pwm. the reason for using leading edge modulation is to leave the trans- former primary side peak current sensing undisturbed. for proper synchronization, the oscillator frequency should be set lower than the system switching frequency with tolerances taken into account. f osc < (f sl ? 0.8) f sl is the low limit of the system switching frequency and 0.8 is the tolerance of f osc . for example, given a system operating at 200khz with 15% tolerance, then f sl = 200khz ? 85% = 170khz; and f osc < (170khz ? 0.8), so f osc should be set below 136khz. once f osc is determined, cset can be calculated by cset = (103540pf/f osc(khz) ) C 18pf. for f osc = 200khz, cset = 500pf. output voltage programming the lt3804 uses true remote sensing (separate ground sensing pins, gnds1 for the first output and gnds2 for the second output) to eliminate output error pickup due to parasitic resistance. the feedback reference voltages v ref1 and v ref2 are 0.6v referred to gnds1 and gnds2 respectively. the output voltage can be easily programmed by a resistor divider, as shown in the block diagram: v out1 = 0.6 (1 + r13/r14) v out2 = 0.6 (1 + r3/r4) where r14 connects to gnds1 and r4 connects to gnds2. for accurate sensing results, gnds1 and gnds2 should stay within C0.1v and 0.1v referred to gnd. note that if either gnds1 or gnds2 is not connected, the lt3804 will be shut down. power good when both outputs reach between 90% and 110% of the programmed level, v pgood goes high( a pull-up resistor is required if the function is used) to signal power good. if either output rises above 110% or drops below 90%, v pgood goes low after a 200 m s delay. pgin1 senses the first output and pgin2 senses the second output with a resistor divider. pgin1 and pgin2 are compared to the references v ref1 and v ref2 respectively. resistor dividers should be connected to gnds1 and gnds2 with respect to each output. current limit ca1 the first output current limit is set by the 50mv threshold across cl1p and cl1n, the inputs of the amplifier ca1. by connecting an external resistor r s1 (see block diagram), the current limit is set for 50mv/r s1 . c17 on i lcomp1 stablizes the current limit loop. if current limit is not used, both cl1p and cl1n should be grounded and c17 is not needed. current limit ca2 the second output current limit is set by the 50mv threshold across cl2p and cl2n, the inputs of the ampli- fier ca2. by connecting an external resistor r s2 (see block diagram), the current limit is set for 50mv/r s2 . r6 and c6 on i lcomp2 stablize the current limit loop. if current limit is not used, both cl2p and cl2n should be grounded and the bgs pin should also be grounded to disable compara- tor ca2; r6 and c6 are not needed. applicatio s i for atio wu u u
lt3804 9 3804i filtering on the sync input a small rc filter with r s = 10k and c s = 10pf is necessary on the sync pin to eliminate fast switching glitches caused by coupling from external components and layout parasitics. optocoupler driver optocoupler driver oa1 is an amplifier with a fixed gain of 6 and can source up to 10ma into the optocoupler. an external resistor is needed from the opto pin to the optocoupler for dc biasing the optocoupler. with a unique 0.3v hysteresis on the threshold v th , oa1 turns into a comparator when it detects output startup or output short. this comparator action jumpstarts the optocoupler to reduce the output overshoot drastically (see figure 3). soft-start and shutdown first output during soft-start, v ss1 is the reference voltage that con- trols the output voltage, so the output ramps up following v ss1 . the effective range of v ss1 is from 0v to v ref1 . the typical time for the output to reach the programmed level is: t = (css1 ? 0.6v)/10 m a figure 3. optocoupler driver applicatio s i for atio wu u u + + v a1 1.5v/ 1.2v v th 15k 90k oa1 1k r opto opto v ref1 0.6v 1.7v 1.4v 1.5v 1.2v 0v 3.3v 2v v out1 v out1 v out1 short v aout1 v aout1 v th v opto opto startup or short release 3804 f03 v fb1 gnds1 r13 2.7k r14 600 5nf 22nf 1k 470 lt3804 to shut down the first output, the ss1 pin should be pulled below 50mv by a small signal vn2222 type n-channel mosfet. soft-start and shutdown second output during soft-start, v ss2 is the reference voltage that con- trols the output voltage, so the output ramps up following v ss2 . the effective range of v ss2 is from 0v to v ref2 . the typical time for the output to reach the programmed level is: t = (css2 ? 0.6v)/10 m a during start up, bgate will stay off until v ss2 reaches 1.6v. this prevents the bottom mosfet from turning on if the output is precharged. to shut down the second output, the ss2 pin should be pulled below 50mv by a small signal vn2222 type n-channel mosfet. note that during shutdown bgate will be locked off when v ss2 drops below 0.6v. this prevents the bottom mosfet from discharging the output, which could cause the output to undershoot below ground.
lt3804 10 3804i output inductor selection the key parameters for choosing the inductor include inductance, rms and saturation current ratings, and dcr. the inductance must be selected to achieve a reasonable value of ripple current, which is determined by: d= i vd fl l out ( ) 1 where v out is the output voltage, d is the duty cycle, f is switching frequency and l is the inductance. typically, the inductor ripple current is designed to be 20% to 40% of the maximum output current. the rms current rating must be high enough to deliver the maximum output current. a sufficient saturation current rating should prevent the inductor core from saturating. these two current ratings can be determined by: ii i ii i rms o lmax sat o lmax 3+ d 3+ d 2 2 12 2 where i o is the maximum dc output current and d i lmax is the maximum peak-to-peak inductor ripple current. to optimize the efficiency, we usually choose the inductor with the minimum dcr if the inductance and current ratings are the same. output n-channel mosfet drivers the lt3804 employs high speed n-channel mosfet synchronous drivers to achieve high system efficiency. gbias is the 8v regulator output to bias and supply the drivers and should be properly bypassed with a low esr applicatio s i for atio wu u u capacitor to the ground plane. a schottky catch diode is required on the switch node. power mosfet selection the lt3804 drives two external n-channel mosfets to deliver high currents at high efficiency. the gate drive voltage is typically 6.5v. the key parameters for choosing mosfets include drain to source voltage rating v dss and r ds(on) at 6.5v gate drive. note that the transformer secondary voltage waveform will overshoot at its rising edge due to the ringing between transformer leakage inductance and parasitic capacitance. the v dss of both top and bottom mosfets must be sufficiently higher than the maximum overshoot. it is recommended that an rc snubber or voltage clamping circuitry be placed across the transformer secondary winding to limit the v s overshoot. the r ds(on) of the mosfets should be selected to deliver the required current at the desired efficiency as well as to meet the thermal requirement of the mosfet package. the conduction power losses of the mosfets are: p m1 @ i o 2 ? r ds(on)m1 ? d p m2 @ i o 2 ? r ds(on)m2 ? (1 C d) where i o is the maximum output current of lt3804 circuit, and r ds(on)m1 and r ds(on)m2 are the on-resistance for the top and bottom mosfets, respectively. the r ds(on) must be determined with 6.5v gate drive at the expected operating temperature. numerous high performance power mosfets are available from siliconix, international rec- tifier and fairchild. if the v dss and r ds(on) ratings are the same, the mosfets with the lowest gate charge q g should be chosen to minimize the power loss associated with the mosfet gate drives, the switching transitions, and the controller bias supply.
lt3804 11 3804i light load operation of second output if the bgs pin is grounded, the lt3804 stays in continuous mode independent of load condition except during soft- start operation (see the soft-start section). if the bgs pin is left open under light load, v rs2 will drop below 8mv, bgate will be turned off(see comparator ca2 of block diagram), and the lt3804 will enter discontinous mode operation. second output capacitor selection the selection of the output capacitor is determined by the output ripple and load transient requirements. in low output voltage applications, always choose capacitors with low esr. the output ripple voltage is approximated by: d?d + ? ? ? ? v i esr fc out l out 1 8 where d i l is the inductor peak-to-peak ripple current. a partial list of low esr high performance capacitor types includes sp capacitors from panasonic and cornell dubilier, poscaps and os-con capacitors from sanyo, t510 and t520 surface mount capacitors from kemet. layout considerations for maximum efficiency, the switching rise and fall times should be less than 20ns. to prevent radiation, the power mosfets, sw pin and input bypass capacitor leads should be kept as short as possible. a ground plane should be used under the switching circuitry to prevent interplane coupling and to act as a thermal spreading path. note that the bottom metal of the package is the heat sink as well as the ic signal ground, and must be soldered to the ground plane. design example figure 4 shows an application example of lt3804. it is a dual output high efficiency isolated dc/dc power supply with 36v to 72v input range, 3.3v/15a and 1.8v/15a outputs. the basic power stage topology is a two-switch forward converter with synchronous rectification. the primary side controller uses an lt3781, a current mode two-switch forward controller with built-in mosfet driv- ers. on the secondary side, the lt3804 is used to provide the voltage feedback for the 3.3v output. the output from the built-in optocoupler driver is fed into an optocoupler (moc207) and then transferred to lt3781 on the primary side to complete the 3.3v regulation. an ltc1693-1 high speed dual n-channel mosfet driver provides the gate drive for the synchronous mosfets at the 3.3v output stage. the ltc1693-1 drivers input signals come from sg and bg outputs of the lt3781 through two small gate drive transformers (t2 and t3). the lt3804 also precisely regulates the 1.8v output by further reducing and controlling the duty cycle of the switching waveform from the power transformer (t1) secondary winding. in fact, the 1.8v circuit is a special synchronous buck converter whose input is a pulsed waveform instead of a dc voltage. true differential remote sensing is provided for both outputs to achieve high regulation accuracies. power good indicator pgood will be high only if both outputs are within 10% of their nominal values. the lt3804 provides current limit function for both 1.8v and 3.3v outputs. the current limits for 3.3v and 1.8v outputs are estimated to be 50mv/r55 and 50mv/r49, respectively. applicatio s i for atio wu u u
lt3804 12 3804i applicatio s i for atio wu u u a planar transformer pa0191 by pulse engineering is employed as the power transformer in this design. this transformer is constructed on a pq20 core with nine turns of primary windings, two turns of secondary windings and seven turns of auxiliary windings for the lt3781 bias supply. si7892dp mosfets are selected for the second- ary side due to their low r ds (on) , 30v v dss rating and compact, thermally enhanced powerpak so-8 package. the switching frequency of the circuit is about 230khz. 1500v input to output isolation is provided. additional features of this design include primary side on/off control, input over voltage protection, under voltage lockout, soft start and board over temperature shutdown. the complete design is mounted within a standard half brick pc board with about half inch height.
lt3804 13 3804i + c8 1000pf 100v c9 1000pf 100v r3 10 1/4w r4 10 1/4w q6 si7892dp 2 q4 si7892dp 2 q1 si7456dp q3 si7456dp c10 2200pf 250v ac r6 3.3 r9, 0.015 1%,1/2w d3 bas21ta d4 bas21ta v cc v cc l2, 1mh do1608c-105 coilcraft l1 1.2 h do1813p-122hc d1 b2100 d1 b2100 v out v ccs r18 100 r17 10k c13 4.7 f 25v r16 2k 0.25w d10 10v mmbz5240b c15 4.7 f 16v d18 b0540w d6 b340a c4 470 f 4v poscap 3 c2 1.5 f 100v 2 l3 1.8 h cep125-1r8 r55 0.003 1% 2512 sec clip clin v o 1 3.3v at 15a v o rtn v o 1 (4tpd470m 3) +v in 36v to 72v ? in vi d4 bat54f c14 330pf q10 zvn3310f r8 10 d12 bat54s r30 1k c19 0.1 f r36 1k c33 10nf r33 6.8k r34 470 d9 bat54 t3 p2033 pulse eng. r29 1k c17 0.1 f r38 1k c16 10nf r32 6.8k r31 470 d8 bat54 t2 p2033 pulse eng. v cc2 out1 out2 gnd2 v cc1 in1 in2 gnd1 ltc1693-1 c21 1 f 16v v ccs c1 0.01 f c29 0.01 f c30 0.015 f c26 6.8nf rt1 100k r37 1k r46 330 r42 2.43k 1% 5v ref 5v ref r39 52.3k 1% c31 1 f c32 82pf v c sgnd ss sync vbst tg bstref bg sense pgnd therm fset v fb sg lt3781 v cc 0vlo shdn 13 2 1 20 19 18 15 11 14 12 9 10 4 8 7 3 6 5 v cc vi r24 270k 0.25w r26 73.2k 1% d17 mmbd4148 d13 bas21ta on off c27 1 f c25 4.7 f 16v c28 1000pf r43 10k r45 1.24k 1% r25 20k vi q7 fzt853 d19 5241b 11v d20 b0540w v cc lt3804 ta02 c6 4.7 f 25v c20 0.1 f 100v 6 7 5 82 4 31 opto c22 4700pf r35 1k 5v ref iso1 moc207 t1 pulse pa0191 q12 fzt690b 8 1 3 2 6 7 5 4 applicatio s i for atio wu u u figure 4. 36v C 72vdc to 3.3v/15a and 1.8v/15a dual output isolated power supply (page 1 of 2)
lt3804 14 3804i opto pgood bgs cset clip clin v aout1 v fb1 gnds1 pgin1 i lcomp1 gbais tgate sw bgate cl2p cl2n v aout2 v fb2 gnds2 pgin2 i lcomp2 sync v cc boost ss1 pgnd ss2 lt3804 27 5 6 26 20 21 15 14 12 11 3 23 19 16 7 1 2 22 18 13 10 28 825 4 17 24 9 opto c37, 680pf c49, 1000pf clip clin c35 180pf c48 180pf c43 0.1 f r12 10k r58 10k c50 1000pf c51 6.8nf r13 1.5k pgood r67 665 1% r66 665 1% r15 3.01k 1% r14 3.01k 1% r19 1k c24 4.7nf vo1 r65 10 vo1s + vo1s v ccs c45 10pf r57 10k r5 100k c44 0.1 f 16v c36 4.7 f 16v d14 cmdsh-3 d15 cmdsh-3 c39 330pf c38 0.033 f r50 3.3k c46 1000pf c47 1 f c42 4700pf v ccs q13 si7892dp q14 si7892dp 2 + l4 1.8 h cep125-1r8 r49 0.003 1% r64 10 r54 3.01k 1% r60 1.5k 1% r62 3.01k 1% r61 1.5k 1% r63 10 c12 680 f 2.5v poscap 3 +v o2 1.8v 15a v o2s v o2s + sec r53 220 3804 ta01 r68 10 (2r5tpd680m 3) from transformer secondary winding 3.3v output remote sense 1.8v output remote sense figure 4. 36v C 72v dc to 3.3v/15a and 1.8v/15a dual output isolated power supply (page 2 of 2) applicatio s i for atio wu u u
lt3804 15 3804i package descriptio u fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation eb fe28 (eb) tssop 0203 0.09 ?0.20 (.0036 ?.0079) 0 ?8 0.45 ?0.75 (.018 ?.030) 4.30 ?4.50* (.169 ?.177) 6.40 bsc 134 5 6 7 8910 11 12 13 14 19 20 22 21 15 16 18 17 9.60 ?9.80* (.378 ?.386) 4.75 (.187) 2.74 (.108) 28 2726 25 24 23 1.20 (.047) max 0.05 ?0.15 (.002 ?.006) 0.65 (.0256) bsc 0.195 ?0.30 (.0077 ?.0118) 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment
lt3804 16 3804i linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2003 lt/tp 0603 1k ? printed in usa related parts part number description comments lt1339 high power synchronous dc/dc controller operation up to 60v maximum lt1425 isolated flyback switching regulator general purpose with external application resistor lt1431 programmable reference 0.4% initial voltage tolerance lt1680 high power dc/dc step-up controller operation up to 60v maximum lt1725 general purpose isolated flyback controller drives external power mosfet with external i sense resistor lt1737 high power isolated flyback controller sense output voltage directly from primary-side winding lt1950 pwm controller for forward, flyback, 3v v in 25v, volt-second clamp, leading-edge blanking, boost and sepic slope compensation lt3710 secondary side synchronous post regulator generates regulated auxiliary output in isolated dc/dc converters, dual n-channel mosfet synchronous drivers ltc3722 synchronous phase modulated full-bridge controller adaptive or manual delay control for zero voltage switching, adjustable maximum zvs delay, current mode and voltage mode. lt3781 dual transistor synchronous forward controller operation up to 72v maximum

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